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Microcomputer Components
8-Bit CMOS Microcontroller
C540U / C541U
Data Sheet 10.97
C540U/C541U Data Sheet Revision History : Previous Releases : Page / Chapters
1997-10-01 none (Original Version)
Subjects (changes since last revision)
Edition 1997-10-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
8-Bit CMOS Microcontroller
C540U C541U
Advance Information
* * * *
*
Enhanced 8-bit C500 CPU - Full software/toolset compatible to standard 80C51/80C52 microcontrollers 12 MHz external operating frequency - 500 ns instruction cycle Built-in PLL for USB synchronization On-chip OTP program memory - C540U : 4K byte - C541U : 8K byte - Alternatively up to 64K byte external program memory - Optional memory protection On-chip USB module - Compliant to USB specification - Full speed or low speed operation - Five endpoints : one bidirectional control endpoint four versatile programmable endpoints - Registers are located in special function register area - On-chip USB transceiver
On-Chip Emulation Support Module
Oscillator Watchdog
Watchdog Timer SSC T0
RAM 256 x 8
Port 0
I/O
Port 1 CPU
I/O
Power Saving Modes
USB Module USB Transceiver D+ D-
T1 OTP Prog. Memory C540U : 4 k x 8 C541U : 8 k x 8
Port 2
I/O
Port 3
I/O
The shaded units are not available in the C540U.
MCA03373
Semiconductor Group
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C540U C541U
Features (cont'd) :
* * *
* *
* * * * * * *
Up to 64K byte external data memory 256 byte on-chip RAM Four parallel I/O ports - P-LCC-44 package : three 8-bit ports and one 6-bit port - P-SDIP-52 package : four 8-bit ports - LED current drive capability for 3 pins (10 mA) Two 16-bit timer/counters (C501 compatible) SSC synchronous serial interface (SPI compatible) (only C541U) - Master and slave capable - Programmable clock polarity / clock-edge to data phase relation - LSB/MSB first selectable - 1.5 MBaud transfer rate at 12 MHz operating frequency 7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels Enhanced fail safe mechanisms - Programmable watchdog timer (only C541U) - Oscillator watchdog Power saving modes - idle mode - software power down mode with wake-up capability through INT0 pin or USB On-chip emulation support logic (Enhanced Hooks Technology TM) P-LCC-44 and P-SDIP-52 packages Power supply voltage range : 4.0V to 5.5V TA = 0 to 70 C Temperature Range : SAB-C540U TA = 0 to 70 C SAB-C541U
Table 1 Ordering Information Type SAB-C540U-EN SAB-C540U-EP SAB-C541U-1EN SAB-C541U-1EP Ordering Code Q67126-C2042 Q67120-C2043 Q67126-C2001 Q67120-C2021 Package P-LCC-44-2 P-SDIP-52-1 P-LCC-44-2 P-SDIP-52-1 Description (8-Bit CMOS microcontroller) 8-Bit CMOS microcontroller (12 MHz) 8-Bit CMOS microcontroller (12 MHz) 8-Bit CMOS microcontroller (12 MHz) 8-Bit CMOS microcontroller (12 MHz)
Semiconductor Group
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C540U C541U
V CC
V SS
XTAL2 XTAL1 ALE PSEN EA RESET D+ DC540U C541U
Port 0 8-Bit Digital I / O Port 1 P-LCC-44 : 6-Bit Digital I / O P-SDIP-52 : 8-Bit Digital I / O Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O
MCL03374
Figure 2 Logic Symbol Additional Literature For further information about the C540U/C541U the following literature is available : Title C540U/C541U 8-Bit CMOS Microcontroller User's Manual C500 Microcontroller Family Architecture and Instruction Set User's Manual C500 Microcontroller Family - Pocket Guide Ordering Number B158-H????-X-X-7600 B158-H6987-X-X-7600 B158-H6986-X-X-7600
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C540U C541U
P1.1 / LED1 P1.0 / LED0 DD+ V SSU V CCU P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 6 5 4 3 2 1 44 43 42 41 40 P1.2 / SCLK V CC V SS RESET P3.0 / LED2 P1.3 / SRI P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13
C540U C541U
18 19 20 21 22 23 24 25 26 27 28 P3.6 / WR P3.7 / RD XTAL2 XTAL1 V SS V CC P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 This pin functionality ist not available for the C540U.
MCP03343
Figure 3 Pin Configuration P-LCC-44 Package (top view)
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C540U C541U
V CCU V SSU
D+ DN.C. N.C. P1.0 / LED0 P1.1 / LED1 P1.2 / SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
N.C. P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO P1.7 ALE PSEN N.C. N.C. P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 N.C.
MCP03344
V CC V SS
RESET P3.0 / LED2 P1.3 / SRI P1.6 P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD XTAL2 XTAL1
C540U C541U
V SS V CC
This pin functionality ist not available for the C540U.
Figure 4 Pin Configuration P-SDIP-52 Package (top view)
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C540U C541U
Table 2 Pin Definitions and Functions Symbol D+ 3 Pin Numbers P-LCC-44 P-SDIP-52 3 I/O USB D+ Data Line The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip). USB D- Data Line The pin D- can be directly connected to USB cable (transceiver is integrated on-chip). Port 1 is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasibidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC (C541U only). The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / LED0 LED0 output P1.1 / LED1 LED1 output P1.2 / SCLK SSC Master Clock Output / SSC Slave Clock Input (C541U only) P1.3 / SRI SSC Receive Input (C541U only) P1.4 / STO SSC Transmit Output (C541U only) P1.5 / SLS SSC Slave Select Inp. (C541U only) P1.6 (P-SDIP-52 only) P1.7 (P-SDIP-52 only) RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C540U/C541U. A small internal pulldown resistor permits power-on reset using only a capacitor connected to VCC . I/O*) Function
D-
4
4
I/O
P1.0 - P1.4
7 - 9, 14, 41, I/O 5 - 7, 12, 34, 44 51, 15, 40
5 6 7 12 34 44 - - RESET 10
7 8 9 13 41 51 15 40 12 I
*) I = Input O = Output
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Table 2 Pin Definitions and Functions Symbol P3.0 - P3.7 Pin Numbers P-LCC-44
(cont'd) I/O*) Function I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / LED2 LED2 output P3.1 / DADD Device attached input External interrupt 0 input / P3.2 / INT0 timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory RD control output; enables the P3.7 / RD external data memory XTAL2 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. XTAL1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.
P-SDIP-52
11, 13 - 19 13, 16 - 22
XTAL2
20
23
-
XTAL1
21
24
-
*) I = Input O = Output
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C540U C541U
Table 2 Pin Definitions and Functions Symbol P2.0 - P2.7 Pin Numbers P-LCC-44 24 - 31
(cont'd) I/O*) Function I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. External Access Enable When held high, the C540U/C541U executes instructions from the internal ROM as long as the PC is less than 1000H for the C540U or less than 2000H for the C541U. When held low, the C540U/ C541U fetches all instructions from external program memory. For the C540U-L/C541U-L this pin must be tied low.
P-SDIP-52 28 - 35
PSEN
32
38
O
ALE
33
39
O
EA
35
42
I
*) I = Input O = Output
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C540U C541U
Table 2 Pin Definitions and Functions Symbol P0.0 - P0.7 Pin Numbers P-LCC-44 44 - 36
(cont'd) I/O*) Function I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Supply voltage for the on-chip USB transceiver circuitry. Ground (0V) for the on-chip USB transceiver circuitry. Supply voltage for ports and internal logic circuitry during normal, idle, and power down mode. Ground (0V) for ports and internal logic circuitry during normal, idle, and power down mode.
P-SDIP-52 50 - 43
VCCU VSSU VCC
1 2 8, 23
1 2 10, 26
- - -
VSS
9, 22
11, 25
-
*) I = Input O = Output
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C540U C541U
Oscillator Watchdog XTAL2 XTAL1 ALE PSEN EA RESET Progr. Watchdog Timer (C541U only) Timer 0 Timer 1 CPU OSC & Timing
RAM 256 x 8
OTP Memory 4k x 8 (C540U) 8k x 8 (C541U)
Emulation Support Logic Port 0 Port 0 8-Bit Digit. I/O Port 1 1) 6- / 8-Bit Digit. I/O Port 2 8-Bit Digit. I/O Port 3 8-Bit Digit. I/O
Port 1 SSC (SPI) Interface (C541U only) Transceiver PLL USB Module Port 2
D+ D-
Port 3
Interrupt Unit
1)
C540U C541U
MCB03345
P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port
Figure 5 Block Diagram of the C540U/C541U
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C540U C541U
CPU The C540U/C541U is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns. Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank Select Control Bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
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C540U C541U
Memory Organization The C540U/C541U CPU manipulates operands in the following four address spaces: - - - - - 8 or 4 KByte on-chip OTP program memory Totally up to 64 Kbyte internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area
Figure 6 illustrates the memory address spaces of the C540U/C541U.
FFFF H
FFFF H
External External Indirect Addr. Internal RAM 2000 H 1) 1FFF H 1) Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "External Data Space" Internal RAM 00 H "Internal Data Space"
MCD03375
FF H
Direct Addr. Special Function Register
FF H
80 H 7F H
80 H
1) For the C504U the int. / ext. program memory boundary is at 0FFF H / 1000 H .
Figure 6 C540U/C541U Memory Map Memory Map
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C540U C541U
Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VCC via a capacitor. Figure 7 shows the possible reset circuitries.
VCC
+
a) C540U C541U RESET
b) C540U C541U RESET
&
VCC
VCC
+
c) C540U C541U RESET
MCD03376
Figure 7 Reset Circuitries
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C540U C541U
The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-8. The crystal oscillator generates the system clock for the microcontroller. The USB module can be provided with the following clocks : - Full speed operation : 48 MHz with a data rate of 12 Mbit/s - Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s The low speed clock is generated by a dividing the system clock by 2. The full speed clock is generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock.
XTAL1 12 MHz XTAL2
Pin Pin
Crystal 12 MHz Oscillator
System Clock of the Microcontroler
Divider by 2 6 MHz
PLL x4 48 MHz 1 0
Enable
PCLK DCR.0
to USB Module SPEED DCR.7 UCLK DCR.1
MCB03377
C540U / C541U
Figure 8 Block Diagram of the Clock Generation Circuitry
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C540U C541U
The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 9 shows the recommended oscillator circuits for crystal and external clock operation.
C XTAL2
12 MHz C
C540U C541U XTAL1
C = 20 pF 10 pF for crystal operation C540U C541U N.C. XTAL2
V CC
External Clock Signal
XTAL1
MCD03378
Figure 9 Recommended Oscillator Circuitries
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C540U C541U
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 10 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens.
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C540U C541U
Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C540U/C541U (PCON1) is located in the mapped special function register area. All other SFRs are located in the standard special function register area. For accessing PCON1 in the mapped special function register area, bit RMAP in special function register SYSCON must be set. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H - Reset Value : XX10XXXXB LSB 0 - SYSCON
6 -
5 EALE
4 RMAP
3 -
2 -
1 -
The functions of the shaded bits are not described in this section.
Bit RMAP
Function Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area (PCON1) is enabled.
As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U are listed in table 3 to table 4. In table 3 they are organized in groups which refer to the functional blocks of the C540U/C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric order of their addresses.
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C540U C541U
Table 3 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP VR0 VR1 VR2 SYSCON IEN0 IEN1 IP0 IP1 ITCON P0 P1 P2 P3 TCON TH0 TH1 TL0 TL1 TMOD SSCCON STB SRB SCF SCIEN SSCMOD Name Accumulator B Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Version Register 0 Version Register 1 Version Register 2 System Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 External Interrupt Trigger Condition Register Port 0 Port 1 Port 2 Port 3 Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Watchdog Timer Control Register Watchdog Timer Reload Register Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H FCH FDH FEH B1H A8H1) A9H B8H 1) B9H) 9AH 80H 1) 90H 1) A0H 1) B0H 1) 88H 1) 8CH 8DH 8AH 8BH 89H 93H 1) 94H 95H ABH 1) ACH 96H C0H 1) 86H 00H 00H 00H 00H 00H 07H C5H C1H YYH 3) XX10XXXXB 2) 0XXX0000B 2) XXXXX000B 2) XXXX0000B 2) XXXXX000B 2) XXXX1010B 2) FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 07H XXH 2) XXH 2) XXXXXX00B 2) XXXXXX00B 2) 00H XXXX0000B 2) 00H
Interrupt System
Ports
Timer 0 / Timer 1
SSC Interface (C541U only)
Watchdog WDCON (C541U WDTREL only)
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01H for the first step) 4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
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Table 3 Special Function Registers - Functional Blocks (cont'd) Block Pow. Sav. Modes USB Module Symbol PCON PCON1 EPSEL USBVAL ADROFF GEPIR DCR DPWDR DIER DIRR FNRL FNRH EPBCn 1) EPBSn 1) EPIEn 1) EPIRn 1) EPBAn 1) EPLENn 1) Name Power Control Register Power Control Register 1 USB Endpoint Select Register USB Data Register USB Address Offset Register USB Global Endpoint Interrupt Request Reg. USB Device Control Register USB Device Power Down Register USB Device Interrupt Control Register USB Device Interrupt Request Register USB Frame Number Register, Low Byte USB Frame Number Register, High Byte USB Endpoint n Buffer Control Register USB Endpoint n Buffer Status Register USB Endpoint n Interrupt Enable Register USB Endpoint n Interrupt Request Register USB Endpoint n Base Address Register USB Endpoint n Buffer Length Register Address Contents after Reset 87H 88H 4) D2H D3H D4H D6H C1H C2H C3H C4H C6H C7H C1H C2H C3H C4H C5H C6H X00X0000B 2) 0XX0XXXXB 2) 80H 00H 00H 2) 00H 000X0000B 00H 00H 00H XXH 00000XXXB 00H 20H 00H 10H 3) 00H 0XXXXXXXB
1) These register are multiple registers (n=0-4) with the same SFR address; selection of register "n" is done by SFR EPSEL. 2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. 3) The reset value of EPIR0 is 11H.
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Reset Bit 7 Value1) 80H 2) P0 81H 82H 83H 86H 4) 87H SP DPL DPH FFH 07H 00H .7 .7 .7 .7 WDT PSEL - TF1 Bit 6 .6 .6 .6 .6 .6 PDS TR1 Bit 5 .5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 SLS MSTR .5 .5 0 - .5 - - - Bit 4 .4 .4 .4 .4 .4 - TR0 WS M0 .4 .4 .4 .4 STO CPOL .4 .4 0 - .4 - - - Bit 3 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 SRI CPHA .3 .3 0 I1ETF .3 ET1 - - Bit 2 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 SCLK BRS2 .2 .2 0 I1ETR .2 EX1 EUDI - Bit 1 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 LED1 BRS1 .1 .1 0 I0ETF .1 ET0 EUEI Bit 0 .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 LED0 BRS0 .0 .0 LSBSM I0ETR .0 EX0 ESSC
00H WDTREL 00H X00X0000B 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH
PCON
88H 2) TCON 88H
2) 3)
PCON1 TMOD TL0 TL1 TH0 TH1
EWPD - GATE .7 .7 .7 .7 .7 SCEN .7 .7 - .7 EA - - C/T .6 .6 .6 .6 .6 TEN .6 .6 - .6 - - -
89H 8AH 8BH 8CH 8DH
90H2) P1
93H 4) SSCCON 07H XXH 94H 4) STB 95H 9AH
4)
96H 4)
XXH SSCMOD 00H ITCON XXXX1010B FFH 0XXX0000B XXXXX000B XXXXXX00B
SRB
LOOPB TRIO
A0H2) P2 A8H2) IEN0 A9H IEN1
ABH SCF
4)
WCOL TC
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is only available in the C541U.
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Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Reset Bit 7 Value1) ACH SCIEN
4)
Bit 6 - WR - - - -
Bit 5 - T1 EALE - - -
Bit 4 - T0 RMAP - - -
Bit 3 - INT1 - PT1 -
Bit 2 - INT0 - PX1 PUDI
Bit 1
Bit 0
XXXXXX00B FFH
- RD - - - -
WCEN TCEN DADD - PT0 PUEI LED2 - PX0 PSSC
4)
B0H2) P3 B1H
SYSCON XX10XXXXB XXXX0000B XXXX0000B XXXX0000B 00H
B8H2) IP0 B9H C0H
2)
IP1
WDCON
OWDS WDTS WDT
SWDT
C1H to C7H D0H
2)
USB Device and Endpoint Register definition see table 3-4 CY EPS7 .7
7)
PSW EPSEL
AC 0 .6 0 0 .6 .6 1 1 .6
F0 0 .5 AO5 0 .5 .5 0 0 .5
RS1 0 .4 AO4 EPI4 .4 .4 0 0 .4
RS0 0 .3 AO3 EPI3 .3 .3 0 0 .3
OV EPS2 .2 AO2 EPI2 .2 .2 1 0 .2
F1 EPS1 .1 AO1 EPI1 .1 .1 0 0 .1
P EPS0 .0 AO0 EPI0 .0 .0 1 1 .0
D2H D3H D4H
80H USBVAL 00H
ADROFF 00H D6H GEPIR 00H E0H2) ACC 00H F0H2) B 00H C5H C1H
6)
0 0 .7 .7 1 1 .7
FCH VR0
3) 5)
FDH VR1
3) 5)
FEH
3) 5)
VR2
1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR respectively bit is only available in the C541U. 5) These are read-only registers 6) The content of this SFR varies with the actual of the step C517A (e.g. 01H for the first step) 7) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
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C540U C541U
Table 5 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) Addr Register Reset Value C1H DCR 000X. 0000B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EPSEL = 1XXX.XXXXB Device Registers
SPEED 0 SE0IE SE0I DA 0 DAIE DAI SWR 0 DDIE DDI SUSP 0 SBIE SBI DINIT 0 SEIE SEI RSM 0 STIE STI UCLK TPWD SUIE SUI PCLK RPWD SOFIE SOFI
C2H DPWDR 00H C3H DIER 00H C4H DIRR C5H reserved C6H FNRL C7H FNRH 00H
FNR7 XXH 0 0000. 0XXXB
FNR6 0
FNR5 0
FNR4 0
FNR3 0
FNR2 FNR10
FNR1 FNR9
FNR0 FNR8
EPSEL = 0XXX.X000B C1H EPBC0 C2H EPBS0 C3H EPIE0 C4H EPIR0 C5H EPBA0 00H 20H 00H 11H
Endpoint 0 Registers
STALL0 0 UBF0 AIE0 ACK0 CBF0 NAIE0 NACK0 0 L06 0 DIR0 RLEIE0 RLE0 0 L05 GEPIE0 ESP0 SOFDE0 INCE0 0 DBM0 SETRD0 SETWR0 CLREP0 DONE0 DNRIE0 NODIE0 EODIE0 SODIE0 DNR0 A06 L03 NOD0 A05 L02 EOD0 A04 L01 SOD0 A03 L00
- -
0 L04
PAGE0 00H C6H EPLEN0 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X001B C1H EPBC1 C2H EPBS1 C3H EPIE1 C4H EPIR1 C5H EPBA1 00H 20H 00H 10H Endpoint 1 Registers
STALL1 0 UBF1 AIE1 ACK1 CBF1 NAIE1 NACK1 0 L16 0 DIR1 RLEIE1 RLE1 0 L15 GEPIE1 ESP1 SOFDE1 INCE1 0 DBM1 SETRD1 SETWR1 CLREP1 DONE1 DNRIE1 NODIE1 EODIE1 SODIE1 DNR1 A16 L13 NOD1 A15 L12 EOD1 A14 L11 SOD1 A13 L10
- -
0 L14
PAGE1 00H C6H EPLEN1 0XXX. 0 XXXXB
C7H reserved
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C540U C541U
Table 5 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont'd) Addr Register Reset Value EPSEL = 0XXX.X010B C1H EPBC2 C2H EPBS2 C3H EPIE2 C4H EPIR2 C5H EPBA2 00H 20H 00H 10H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Endpoint 2 Registers
STALL2 0 UBF2 AIE2 ACK2 CBF2 NAIE2 NACK2 0 L62 0 DIR2 RLEIE2 RLE2 0 L52 GEPIE2 ESP2 SOFDE2 INCE2 0 DBM2 SETRD2 SETWR2 CLREP2 DONE2 DNRIE2 NODIE2 EODIE2 SODIE2 DNR2 A62 L32 NOD2 A52 L22 EOD2 A42 L12 SOD2 A32 L02
- -
0 L42
PAGE2 00H C6H EPLEN2 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X011B C1H EPBC3 C2H EPBS3 C3H EPIE3 C4H EPIR3 C5H EPBA3 00H 20H 00H 10H Endpoint 3 Registers
STALL3 0 UBF3 AIE3 ACK3 CBF3 NAIE3 NACK3 0 L63 0 DIR3 RLEIE3 RLE3 0 L53 GEPIE3 ESP3 SOFDE3 INCE3 0 DBM3 SETRD3 SETWR3 CLREP3 DONE3 DNRIE3 NODIE3 EODIE3 SODIE3 DNR3 A63 L33 NOD3 A52 L23 EOD3 A43 L13 SOD3 A33 L03
- -
0 L43
PAGE3 00H C6H EPLEN3 0XXX. 0 XXXXB
C7H reserved EPSEL = 0XXX.X100B C1H EPBC4 C2H EPBS4 C3H EPIE4 C4H EPIR4 C5H EPBA4 00H 20H 00H 10H Endpoint 4 Registers
STALL4 0 UBF4 AIE4 ACK4 CBF4 NAIE4 NACK4 0 L64 0 DIR4 RLEIE4 RLE4 0 L54 GEPIE4 ESP4 SOFDE4 INCE4 0 DBM4 SETRD4 SETWR4 CLREP4 DONE4 DNRIE4 NODIE4 EODIE4 SODIE4 DNR4 A64 L34 NOD4 A54 L24 EOD4 A44 L14 SOD4 A34 L04
- -4
0 L44
PAGE4 00H C6H EPLEN4 0XXX. 0 XXXXB
C7H reserved
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C540U C541U
Digital I/O Ports The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package port 1 is a 6-bit I/O port only. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the capability of driving external LEDs in the output low state.
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C540U C541U
Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops TMOD M1 0 1 1 1 M0 0 1 0 1 internal Input Clock external (max)
fOSC/6x32
fOSC/12x32
fOSC/6
fOSC/12
In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/6. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the input clock logic.
OSC
/6 C/T = 0
f OSC /6
Timer 0/1 Input Clock C/T = 1
P3.4/T0 P3.5/T1 TR0 TR1
_ <1
Control &
Gate (TMOD) P3.2/INT0 P3.3/INT1
=1
MCS03117
Figure 11 Timer/Counter 0 and 1 Input Clock Logic Semiconductor Group 27 1997-10-01
C540U C541U
SSC Interface (C541U only) The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 12 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB.
Pin
P1.2 / SCLK
f OSC
Pin Clock Divider ... Clock Selection Shift Register SRB Receive Buffer Register Interrupt Pin P1.5 / SLS STB Pin Control Logic P1.3 / SRI
Pin
P1.4 / STO
SCIEN Int. Enable Reg. SSCCON Control Register Status Register Control Logic SCF
Internal Bus
MCB03379
Figure 12 SSC Block Diagram The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2/ SCLK. When operating in slave mode, a slave select input is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P1.5 / SLS. The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals.
Semiconductor Group
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C540U C541U
USB Module The USB module in the C540U/C541U handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB memory with two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU memory access control, the UDC device core for USB protocol handling, the microcontroller interface with the USB specific special function registers and the interrupt control logic. A clock generation unit provides the clock signal for the USB module for full speed and low speed USB operation. Figure 13 shows the block diagram of the functional units of the USB module with their interfaces.
XTAL1 Pin
XTAL2 Pin
USB D+ Pin
Bus DPin
Osc. 12 MHz
Page 1
7F H
7F H
Transceiver (On-chip) x4 PLL 48 MHz 2 6 MHz
USB Module
Page 0 USB Memory (128 x 8) 00 H
00 H Internal Bus
Data USB Device Core (UDC) Control
Data Address MMU USB Memory Management Control
MCU Interface
11 SFR Addr.
Interrupt Generation
MCB03380
Figure 13 USB Module Block Diagram
Semiconductor Group
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1997-10-01
C540U C541U
USB Registers Two different kinds of registers are implemented in the USB module. The global registers (GEPIR, EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are needed to control the USB module inside the C540U/C541U, device registers and endpoint registers are mapped into an SFR address block of seven SFR addresses (C1H to C7H). The endpoint specific functionality of the USB module is controlled via the device registers DCR, DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is available for each endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure 14 explains the structure of the USB module registers.
Global Registers GEPIR (D6 H ) 0 0 0 .4 .3 .2 .1 .0 ADROFF (D4 H ) 0 0 .5 .4 .3 .2 .1 .0
USBVAL (D3 H ) EPSEL (D2 H )
.7 .6 .5 .4 .3 .2 .1 .0
.7 0 0 0 0 .2 .1 .0 Decoder
Device Registers C1 H C3 H C4 H C6 H C7 H DCR
Endpoint 0 Registers C1 H EPBC0 C2 H EPBS0 C3 H C4 H EPIE0 EPIR0
Endpoint 1 Registers C1 H EPBC1 C2 H EPBS1 C3 H C4 H EPIE1 EPIR1
Endpoint 2 Registers C1 H EPBC2 C2 H EPBS2 C3 H C4 H EPIE2 EPIR2
Endpoint 3 Registers C1 H EPBC3 C2 H EPBS3 C3 H C4 H EPIE3 EPIR3
Endpoint 4 Registers C1 H EPBC4 C2 H EPBS4 C3 H C4 H EPIE4 EPIR4
C2 H DPWDR DIER DIRR
C5 H reserved FNRL FNRH
C5 H EPBA0 C6 H EPLEN0 C7 H reserved
C5 H EPBA1 C6 H EPLEN1 C7 H reserved
C5 H EPBA2 C6 H EPLEN2 C7 H reserved
C5 H EPBA3 C6 H EPLEN3 C7 H reserved
C5 H EPBA4 C6 H EPLEN4 C7 H reserved
MCD03312
Figure 14 Register Structure of the USB Module
Semiconductor Group
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1997-10-01
C540U C541U
Interrupt System The C541U provides seven (C540U : six) interrupt sources with two priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, SSC interface, and USB module), and two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1). Figure 15 to 17 give a general overview of the interrupt sources and illustrate the request and control flags which are described in the next sections.
Low Priority Timer 0 Overflow TF0 TCON.5 ET0 IEN0.1 Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 P3.2 / INT0 IT0 TCON.0 ITCON.1 ITCON.0 1 IE0 TCON.1 EX0 IEN0.0 0003H PX0 IP0.0 001BH PT1 IP0.3 000BH PT0 IP0.1 High Priority
P3.3 / INT1 IT1 TCON.2 ITCON.3 Bit addressable ITCON.2
1 IE0 TCON.3 EX1 IEN0.2 EA IEN0.7 0013H PX1 IP0.2
Request Flag is cleared by hardware
Figure 15 Interrupt Request Sources (Part 1)
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C540U C541U
Endpoint Interrupts
Endpoint 4 Interrupts Endpoint 3 Interrupts Endpoint 2 Interrupts Endpoint 1 Interrupts Endpoint 0 Interrupts ACK0 EPIR0.7
NACK0
AIE0 EPIE0.7 NAIE0 EPIE0.6 RLEIE0 EPIE0.5 DNRIE0 EPIE0.3 NODIE0 EPIE0.2 EODIE0 EPIE0.1 SODIE0 EPIE0.0 GEPIE0
EPIR0.6 RLE0 EPIR0.5 DNR0 EPIR0.3 NOD0 EPIR0.2 EOD0 EPIR0.1 SOD0 EPIR0.0
>1 EPI0 GEPIR.0 >1 Low Priority High Priority EUEI IEN1.1 EPBC0.4 004B H PUEI IP1.1
WCOL SSC Interrupts (C541U only) SCF.1 WCEN SCIEN.1 ESSC TC SCF.0 Bit addressable Request flag is cleared by hardware after the corresponding register has been read.
MCB03382
>1
0043 H PSSC EA IEN0.7 IP1.0
IEN1.0 TCEN SCIEN.0
Figure 16 Interrupt Request Sources (Part 2)
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1997-10-01
C540U C541U
Device Interrupts
SE0I DIRR.7 DAI DIRR.6 DDI DIRR.5 SBI DIRR.4 SEI DIRR.3 STI DIRR.2 SUI DIRR.1 SOFI DIRR.0
SE0IE DIER.7 DAIE DIER.6 DDIE DIER.5 SBIE DIER.4 SEIE DIER.3 STIE DIER.2 SUIE DIER.1 SOFIE DIER.0
>1 Low Priority High Priority EUDI IE1.2 0053 H PUDI IP1.2
EA IE0.7
Bit addressable Request flag is cleared by hardware after the corresponding register has been read.
MCB03383
Figure 17 Interrupt Request Sources (Part 3) Table 7 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow SSC Interrupt (C541U only) USB Endpoint Interrupt USB Device Interrupt Wake-up from power down Interrupt Vector Address 0003H 000BH 0013H 001BH 0043H 004BH 0053H 007BH Interrupt Request Flags (SFRs) IE0 TF0 IE1 TF1 TC, WCOL in SFRs EPIR0-4 and GEIPR in SFRs DIRR -
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C540U C541U
Fail Save Mechanisms The C540U/C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : - a programmable watchdog timer (WDT), with variable time-out period from 256 s up to approx. 0.55 s at 12 MHz. The WDT is not available in the C540U. - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of fOSC/12 or fOSC/192. The system clock of the C517A is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-18 shows the block diagram of the watchdog timer unit.
0
7 WDTL 14 8 WDTH
f OSC / 6
2
16
WDT Reset-Request WDCON (CO H ) -
-
-
OWDS WDTS
WDT
SWDT
WDTPSEL
Control Logic 76 External HW Reset WDTREL
MCB03384
0
Figure 18 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active mode of the C541U. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor.
Semiconductor Group
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C540U C541U
Oscillator Watchdog The oscillator watchdog unit serves for three functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Control of external wake-up from software power-down mode (description see chapter 9) When the power-down mode is left by a low level at the INT0 pin or by the USB, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the powerdown wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
Semiconductor Group
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1997-10-01
C540U C541U
EWPD (PCON1.7) Activity on USB Bus P3.2 / INT0 Control Logic
WS (PCON1.4)
Power - Down Mode Activated Power-Down Mode Wake - Up Interrupt Control Logic Internal Reset
Start / Stop RC Oscillator
f RC
3 MHz Start / Stop
10
f1
Frequency Comparator
f 2 Delay
>1
XTAL1 XTAL2 On-Chip Oscillator
f2
WDCON (C0 H )
OWDS
Int. Clock
MCD03385
Figure 19 Functional Block Diagram of the Oscillator Watchdog
Semiconductor Group
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1997-10-01
C540U C541U
Power Saving Modes The C540U/C541U provides two basic power saving modes, the idle mode and the power down mode. - Idle mode In the idle mode the main oscillator of the C540U/C541U continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the SSC (C541U only), the USB module, and the timers with the exception of the watchdog timer (C541U only) are further provided with the clock. The CPU status is preserved in its entirety : the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The idle mode can be terminated by activating any enabled interrupt. or by a hardware reset. - Power down mode In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The power down mode can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity on the USB bus. Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the state of the SFRs, which has been frozen when power down mode is entered. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level, before the power down mode is terminated. Table 8 gives a general overview of the entry and exit procedures of the power saving modes. Table 8 Power Saving Modes Overview Mode Entering 2-Instruction Example ORL PCON, #01H ORL PCON, #20H Leaving by Remarks
Idle mode
Ocurrence of an interrupt from a peripheral unit Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Oscillator is stopped; contents of on-chip RAM and SFR's are maintained;
Power Down Mode
ORL PCON, #02H ORL PCON, #40H
Hardware Reset Short low pulse at pin P3.2/INT0 or activity on the USB bus
Semiconductor Group
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1997-10-01
C540U C541U
OTP Memory Operation The C540U/C541U contains a 8k byte one-time programmable (OTP) program memory (C540U : 4k byte). With the C540U/C541U fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be selected. For programming of the device, the C540U/C541U must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C540U/C541U operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5V programming voltage. Figure 20 shows the pins of the C504-2E which are required for controlling of the OTP programming mode.
V CC
V SS
A0 - A7 / A8 - A12 PALE PMSEL0 PMSEL1
Port 2
Port 0
D0 - D7
EA / V PP
C540U C541U
PROG PRD RESET
XTAL1 XTAL2
PSEN PSEL
MCS03386
Figure 20 Programming Mode Configuration
Semiconductor Group
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1997-10-01
C540U C541U
Pin Configuration in Programming Mode
N.C. N.C. N.C. N.C. N.C. N.C. N.C. D0 D1 D2 D3
6 5 4 3 2 1 44 43 42 41 40 N.C. V CC V SS RESET PMSEL0 N.C: PMSEL1 PSEL PRD PALE GND 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 D4 D5 D6 D7 EA / V PP N.C. PROG PSEN A7 A6 A5
C540U C541U Programming Mode
18 19 20 21 22 23 24 25 26 27 28
A0 / A8 A1 / A9 A2 / A10 A3 / A11 A4 / A12 GND GND XTAL2 XTAL1 V SS V CC
MCP03387
Figure 21 P-LCC-44 Pin Configuration of the C540U/C541U in Programming Mode (Top View)
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1997-10-01
C540U C541U
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V CC V SS RESET PMSEL0 N.C. N.C. PMSEL1 PSEL PRD PALE GND GND GND XTAL2 XTAL1 V SS V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
C540U C541U Programming Mode
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
N.C. P1.5 / SLS D0 D1 D2 D3 D4 D5 D6 D7 EA / V PP N.C. N.C. PROG PSEN N.C. N.C. A7 A6 A5 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 N.C.
MCP03388
Figure 22 P-SDIP-52 Pin Configuration of the C540U/C541U in Programming Mode (Top View)
Semiconductor Group
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C540U C541U
The following table 9 contains the functional description of all C517A-2E pins which are required for OTP memory programming. Table 9 Pin Definitions and Functions in Programming Mode Symbol RESET 10 Pin Numbers P-LCC-44 P-SDIP-52 12 I Reset This input must be at static "1" (active) level during the whole programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL PMSEL Access Mode 1 0 0 0 1 1 PSEL 14 17 I 0 1 0 1 Reserved Read version bytes Program/read lock bits Program/read OTP memory byte I/O*) Function
PMSEL0 PMSEL1
11 13
13 16
I I
Basic programming mode select This input is used for the basic programming mode selection and must be switched according figure 1023. Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. Programming mode address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/ from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier.
PRD
15
18
I
PALE
16
19
I
XTAL2
20
23
O
*) I = Input O = Output
Semiconductor Group
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1997-10-01
C540U C541U
Table 9 Pin Definitions and Functions in Programming Mode (cont'd) Symbol XTAL1 A0/A8 A7 21 24 - 31 Pin Numbers P-LCC-44 P-SDIP-52 24 28 - 35 I I XTAL1 Input to the oscillator amplifier. Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A12. A8-A12 must be latched with PALE. Address A12 is requred only for the C541U. Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG. External Access / Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level (VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are read or written from or to the C540U/C541U via the bidirectional D0-7 lines which are located at port 0. Circuit ground potential must be applied to these pins in programming mode. Power supply terminal must be applied to these pins in programming mode. Not Connected These pins should not be connected in programming mode. Ground pins In programming mode these pins must be connected to VIL level. I/O*) Function
PSEN
32
38
I
PROG
33
39
I
EA/VPP
35
42
I
D0 - 7
43 - 38
50 - 43
I/O
VSS VCC
N.C.
9, 22 8, 23 1, 12,, 34, 44
11, 25 10, 26 1 - 9, 14, 15, 27, 36, 37, 40, 41, 52 20 - 22
- - -
GND
17 - 19
I
*) I = Input O = Output
Semiconductor Group
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1997-10-01
C540U C541U
Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 23.
V CC
Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1" "0"
5V
V PP
EA / V PP During this Period Signals are not actively driven 0V
V IH1
Ready for Access Mode Selection
MCT03389
Figure 23 Basic Programming Mode Selection
Semiconductor Group
43
1997-10-01
C540U C541U
Table 10 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte EA/ VPP VPP VIH VPP VIH VIH H H L H Byte addr. of sign. byte H H H L PROG PRD H PMSEL 1 H 0 H Address (Port 2) A0-7 A8-15 - Data (Port 0) D0-7 D1,D0 see table 11 D0-7
Lock Bits Programming / Read The C540U/C541U has two programmable lock bits which, when programmed according tabie 11, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 11 Lock Bit Protection Types Lock Bits at D1,D0 D1 1 D0 1 Protection Protection Type Level Level 0 The OTP lock feature is disabled. During normal operation of the C540U/C541U, the state of the EA pin is not latched on reset. During normal operation of the C540U/C541U, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible using the OTP verification mode for protection level 1. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using OTP verification mode is disabled. Same as level 2; but additionally external code execution by setting EA=low during normal operation of the C540U/C541U is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.
1
0
Level 1
0 0
1 0
Level 2 Level 3
Semiconductor Group
44
1997-10-01
C540U C541U
Absolute Maximum Ratings Ambient temperature under bias (TA) ......................................................... Storage temperature (Tstg) .......................................................................... Voltage on VCC pins with respect to ground (VSS) ....................................... Voltage on any pin with respect to ground (VSS) ......................................... Input current on any pin during overload condition..................................... Absolute sum of all input currents during overload condition ..................... Power dissipation........................................................................................ 0 to 70 C - 65 C to 150 C - 0.5 V to 6.5 V - 0.5 V to VCC +0.5 V - 10 mA to 10 mA I 100 mA I TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Semiconductor Group
45
1997-10-01
C540U C541U
DC Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Symbol min.
TA = 0 to 70 C
Limit Values max. 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 V V V V V V V V V V V A A A pF mA - - - - - - - 0.5 - 0.5 - 0.5 0.2 VCC + 0.9 0.7 VCC 0.6 VCC - - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - - - 10.9 Unit Test Condition
VIL VIL1 VIL2
Input high voltage (except XTAL1, VIH RESET) Input high voltage to XTAL1 Input high voltage to RESET Output low voltage Ports 1, 2, 3 P1.0, P1.1, P3.0 Output low voltage (port 0, ALE, PSEN)
VCC + 0.5 VCC + 0.5 VCC + 0.5
0.45 0.45 0.45 - - - - - 50 - 650 1 10
VIH1 VIH2 VOL VOL1
IOL = 1.6 mA 1) IOL = 10 mA 1) IOL = 3.2 mA 1) IOH = - 80 A, IOH = - 10 A IOH = - 800 A IOH = - 80 A 2) VIN = 0.45 V VIN = 2 V
0.45 < VIN < VCC
Output high voltage (ports 1, 2, 3) VOH Output high voltage (port 0 in external bus mode, ALE, PSEN) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Overload current Programming voltage Notes see next page
VOH2
Logic 0 input current (ports 1, 2, 3) IIL
ITL ILI CIO IOV VPP
fc = 1 MHz, TA = 25 C 7)
6) 7)
5
12.1
V
11.5 V 5%
Semiconductor Group
46
1997-10-01
C540U C541U
Power Supply Current Parameter Active mode Idle mode Power-down mode
Notes : 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VCC ; XTAL2 = N.C.; XTAL1 = VSS ; RESET = VSS; all other pins are disconnected. the USB transceiver is switched off; 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = RESET = Port 0 = Port 1 = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = RESET = Vss ; Port 0 = VCC ; all other pins are disconnected; 6) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 7) Not 100% tested, guaranteed by design characterization. 8) The typical ICC values are periodically measured at TA = +25 C but not 100% tested. 9) The maximum ICC values are measured under worst case conditions (TA = 0 C and VCC = 5.5 V)
Symbol 12 MHz 12 MHz
Limit Values typ. 8) max. 9) TBD TBD 50 15 TBD TBD
Unit Test Condition mA mA A
4) 5)
ICC ICC IPD
VCC = 2...5.5 V 3)
Semiconductor Group
47
1997-10-01
C540U C541U
AC Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Program Memory Characteristics Parameter Symbol
TA = 0 to 70 C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Limit Values 10-MHz clock Duty Cycle 0.4 to 0.6 min. max. - - - 80 - - 51 - 23 - 140 Variable Clock 1/CLP = 2 MHz to 12 MHz **) min. CLP - 40 max. -
Unit
ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
*)
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV tAVIV tAZPL
*)
43 13 13 - 13 86 - 0 - 28 - 0
ns ns ns ns ns ns
TCLHmin -20 - TCLHmin -20 - - 2 CLP - 87 TCLLmin -20 - CLP+ - TCLHmin -30 - 0 - TCLLmin - 5 - 0
CLP+ ns TCLHmin- 65 - - ns ns TCLLmin -10 ns 2 CLP + ns TCLHmin -60 - ns
Interfacing the C540U/C541U to devices with float times up to 28 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The microcontroller (except the USB module) operates down to 2 MHz.
**)
Semiconductor Group
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1997-10-01
C540U C541U
AC Characteristics (cont'd) External Data Memory Characteristics Parameter Symbol 10-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 110 Limit Values Variable Clock 1/CLP= 2 MHz to 12 MHz Unit
min. 3 CLP - 70 3 CLP - 70 CLP - 27 - 0
max. - - - 2 CLP+ TCLHmin - 90 - CLP - 20 4 CLP - 133 4 CLP + TCLHmin -155 CLP+ TCLLmin+ 50 - TCLHmin + 25 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
180 180 56 - 0 - - - 66 70 8 8 163 8 -
63 200 211 166 - 58 - - - 0
- - - CLP + TCLLmin - 50 2 CLP - 97 TCLHmin - 25 TCLLmin - 25
3 CLP + - TCLLmin - 120 TCLHmin - 25 - - 0
Semiconductor Group
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1997-10-01
C540U C541U
AC Characteristics (cont'd) External Clock Drive Characteristics Parameter Symbol CPU Clock = 12 MHz Duty cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 83.3 33 33 - - 0.4 33 max. 83.3 - - 12 12 0.6 50 Variable CPU Clock 1/CLP = 2 to 12 MHz min. 83.3 33 33 - - 33 / CLP CLP * DCmin max. 500 CLP-TCLL CLP-TCLH 12 12 1 - 33 / CLP ns ns ns ns ns - Unit
tR tF
DC TCL
CLP * DCmax ns
SSC Interface Characteristics Parameter Clock Cycle Time : Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay SLS low to first SCLK clock edge SLS low to STO active SLS high to STO tristate Data output delay (already defined) Symbol min. Limit Values max. - - - - 100 - - - 8 CLP - - 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 667 667 300 300 - 0 100 50 - 2 tCLCL Unit
tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC tSC tTS tST tD
Last SCLK clock edge to SLS high tCS
tCLCL
0 - -
Semiconductor Group
50
1997-10-01
C540U C541U
t LHLL
ALE
t AVLL t
LLIV
t PLPH t LLPL t PLIV
PSEN
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 24 Program Memory Read Cycle
Semiconductor Group
51
1997-10-01
C540U C541U
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 25 Data Memory Read Cycle
Semiconductor Group
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1997-10-01
C540U C541U
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 26 Data Memory Write Cycle
TCL H
tR
tF
XTAL1
TCL L CLP
0.7 V CC 0.2 V CC - 0.1
MCT03310
Figure 27 External Clock Drive on XTAL1
Semiconductor Group
53
1997-10-01
C540U C541U
t SCLK t SCL
SCLK
t SCH
tD
STO MSB
t HD
~ ~
LSB
tS
SRI
t HI
MSB
~ ~
~ ~
~ ~
LSB
~ ~
t DTC
TC
~ ~
MCT02417
Notes :
Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Figure 28 SSC Master Mode Timing
Semiconductor Group
54
1997-10-01
C540U C541U
t SCLK
t SCH
t SCL
SCLK (CPOL = 1)
SCLK (CPOL = 0)
t SC
SLS
t CS t ST
t TS
STO (CPHA = 0) DOUT 7
tD
tD
DOUT 0
tD
tD
STO (CPHA = 1) DOUT 7 DOUT 1
tD
DOUT 0
MCT03390
Figure 29 SSC Slave Mode Timing
Semiconductor Group
55
1997-10-01
C540U C541U
AC Characteristics of Programming Mode
VCC = 5 V 10 %; VPP = 11.5 V 5 %; TA = 25 C 10 C
Parameter ALE pulse width PMSEL setup to ALE rising edge Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - ns ns ns ns ns ns s ns ns ns ns ns s ns 500 ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 83.3 Unit
tPAW tPMS
Address setup to ALE, PROG, or PRD falling tPAS edge Address hold after ALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD
tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF
PROG high between two consecutive PROG tPWH1 low pulses PRD high between two consecutive PRD low tPWH2 pulses XTAL clock period
tCLKP
Semiconductor Group
56
1997-10-01
C540U C541U
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A13
t PAH
A0-A7
Port 0
D0-D7
PROG
t PWH t PCS t PWW t PCH
MCT03369
Figure 30 Programming Code Byte - Write Cycle Timing
Semiconductor Group
57
1997-10-01
C540U C541U
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-13
t PAH
A0-7
t PAD
Port 0 D0-7
t PDH
t PRD
PRD
t PDF t PWH
t PCS
Notes: PROG must be high during a programming read cycle.
t PRW
t PCH
MCT03392
Figure 31 Verify Code Byte - Read Cycle Timing
Semiconductor Group
58
1997-10-01
C540U C541U
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCS t PMS
PROG
t PCH t PMH t PDH t PWW t PMS t PRD t PRW t PMH t PDF
PRD Note: PALE should be low during a lock bit read / write cycle.
MCT03393
Figure 32 Lock Bit Access Timing
PMSEL1,0
L, H
Port 2
e. g. FD H
t PCH
Port 0 D0-7
t PCS t PRD t PMS
PRD
t PDH t PDF t PMH
t PRW
Note: PROG must be high during a programming read cycle.
MCT03394
Figure 33 Version Byte Read Timing
Semiconductor Group
59
1997-10-01
C540U C541U
OTP Verification Characteristics OTP Verification Mode for Protection Level 1 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. - - 4 tCLCL - - 6 ns ns ns ns ns MHz - - - 8 tCLCL - 4 Unit
tAWD tACY tDVA tDSA tAS
1/tCLCL
tCLCL
-
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 34 OTP Verification Mode for Protection Level 1
Semiconductor Group
60
1997-10-01
C540U C541U
USB Transceiver Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Parameter Output impedance (high state) Output impedance (low state) Input leakage current Tristate output off-state current Crossover point
Notes :
TA = 0 to 70 C
Limit Values min. max. 43 51 5 10 2.0 A A V
1)
Symbol
Unit
Test Condition
RDH RDL II I OZ VCR
28 28 - - 1.3
VIN = VSS or VCC VOUT = VSS or VCC 1)
2)
1) This value includes an external resistor of 30 1% (see "Load for D+/D-" diagram for testing details) 2) The crossover point is in the range of 1.3V to 2.0V for the high speed mode with a 50pF capacitance. In the low-speed mode with a 100pF or greater capacitance, the crossover point is in the range of 1.3V to 2.0V.
Parameter High speed mode rise time High speed mode fall time Low speed mode rise time Low speed mode fall time
Symbol min.
Limit Values max. 20 20 300 300 4 4 75 75
Unit ns ns ns ns
tFR tFF tLR tLF
Semiconductor Group
61
1997-10-01
C540U C541U
VCC -0.5 V
0.2 VCC+0.9 Test Points 0.2 VCC -0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 35 AC Testing: Input, Output Waveforms
VOH -0.1 V
Timing Reference Points
VLoad +0.1 V VLoad VLoad -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 36 AC Testing : Float Waveforms
2.8 V Test Point 1.5 k *)
30 k D.U.T 15 k
S1
CL
Test S1 Close Open Open Close
MCS03425
C L = 50 pF, full speed C L = 50 pF, low speed (min. timing) C L = 350 pF, low speed (max. timing) *) 1.5 k on D- (low speed) or D+ (full speed) only
D- / LS D+ / LS D- / FS D+ / FS
Figure 37 Load for D+/DSemiconductor Group 62 1997-10-01
C540U C541U
Crystal Oscillator Mode C XTAL2 2 - 12 MHz XTAL1 C Crystal Mode: C = 20 pF 10 pF (Incl. Stray Capacitance)
Driving from External Source N.C. XTAL2
External Oscillator Signal
XTAL1
MCS03426
Figure 38 Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
63
1997-10-01
C540U C541U
Plastic Package, P-LCC-44-1 (SMD) (Plastic Leaded Chip Carrier Package)
Figure 39 P-LCC-44-1 Package Outline
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 64
Dimensions in mm 1997-10-01
GPL05102
C540U C541U
Plastic Package, P-SDIP-52-1 (Plastic Shrink Dual In-Line Package)
Figure 40 P-SDIP-52-1 Package Outline
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" Dimensions in mm Semiconductor Group 65 1997-10-01
GPD05262

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